Digital System Design with VHDL

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Название: Digital System Design with VHDL

Автор: Zwolinski M.

Издательство: Prentice Hall

Год: 2004

Страниц: 384

ISBN: 013039985X, 9780130399854, 9781405890977

Формат: PDF

Размер: 22.6 Мб

Язык: English

Since the publication of the first edition, a new version of the VHDL standard has been agreed and analogue extensions to the language have also been adopted. The second edition of Digital System Design with VHDL includes additions in two important areas; sections on writing testbenches have been added to relevant chapters, and the addition of a new chapter on VHDL-AMS and mixed-signal modeling.

The unique approach will be appreciated by undergraduates in Electronic Engineering and Computer Engineering in all years of their courses and by students undertaking postgraduate study. There is also a proven need from industry for graduates with knowledge of VHDL and the associated design tools and this book will be an asset to engineers who wish to continue their studies.

Contents

Preface ix

1 Introduction 1

1.1 Modern digital design 1

1.2 CMOS technology 5

1.3 Programmable logic 10

1.4 Electrical properties 14

Summary 18

Further reading 18

Exercises 18

2 Combinational logic design 19

2.1 Boolean algebra 19

2.2 Logic gates 22

2.3 Combinational logic design 22

2.4 Timing 30

2.5 Number codes 32

Summary 36

Further reading 36

Exercises 36

3 Combinational logic using VHDL gate models 38

3.1 Entities and architectures 38

3.2 Identifiers, spaces and comments 40

3.3 Netlists 41

3.4 Signal assignments 44

3.5 Generics 45

3.6 Constant and open ports 47

3.7 Testbenches 48

3.8 Configurations 48

Summary 51

Further reading 51

Exercises 51

4 Combinational building blocks 53

4.1 Three-state buffers 53

4.2 Decoders 58

4.3 Multiplexers 64

4.4 Priority encoder 66

4.5 Adders 69

4.6 Parity checker 72

4.7 Testbenches for combinational blocks 75

Summary 78

Further reading 78

Exercises 78

5 Synchronous sequential design 80

5.1 Synchronous sequential systems 80

5.2 Models of synchronous sequential systems 81

5.3 Algorithmic state machines 85

5.4 Synthesis from ASM charts 89

5.5 State machines in VHDL 99

5.6 VHDL testbenches for state machines 109

Summary 111

Further reading 112

Exercises 112

6 VHDL models of sequential logic blocks 115

6.1 Latches 115

6.2 Flip-flops 119

6.3 JK and T flip-flops 128

6.4 Registers and shift registers 132

6.5 Counters 135

6.6 Memory 143

6.7 Sequential multiplier 147

6.8 Testbenches for sequential building blocks 150

Summary 153

Further reading 154

Exercises 154

7 Complex sequential systems 156

7.1 Linked state machines 156

7.2 Datapath/controller partitioning 160

7.3 Instructions 162

7.4 A simple microprocessor 163

7.5 VHDL model of a simple microprocessor 167

Summary 176

Further reading 177

Exercises 177

8 VHDL simulation 178

8.1 Event-driven simulation 178

8.2 Simulation of VHDL models 182

8.3 Simulation modelling issues 185

8.4 File operations 186

Summary 188

Further reading 188

Exercises 188

9 VHDL synthesis 190

9.1 RTL synthesis 191

9.2 Constraints 203

9.3 Synthesis for FPGAs 206

9.4 Behavioural synthesis 209

9.5 Verifying synthesis results 216

Summary 218

Further reading 218

Exercises 218

10 Testing digital systems 221

10.1 The need for testing 221

10.2 Fault models 222

10.3 Fault-oriented test pattern generation 224

10.4 Fault simulation 231

10.5 Fault simulation in VHDL 235

Summary 244

Further reading 245

Exercises 245

11 Design for testability 248

11.1 Ad hoc testability improvements 249

11.2 Structured design for test 249

11.3 Built-in self-test 252

11.4 Boundary scan (IEEE 1149.1) 260

Summary 268

Further reading 268

Exercises 268

12 Asynchronous sequential design 271

12.1 Asynchronous circuits 271

12.2 Analysis of asynchronous circuits 274

12.3 Design of asynchronous sequential circuits 278

12.4 Asynchronous state machines 286

12.5 Setup and hold times and metastability 290

Summary 297

Further reading 298

Exercises 298

13 Interfacing with the analogue world 301

13.1 Digital to analogue converters 302

13.2 Analogue to digital converters 303

13.3 VHDL-AMS 306

13.4 Phase-locked loops 315

13.5 VHDL-AMS simulators 319

Summary 321

Further reading 321

Exercises 321

Appendix A VHDL standards 322

Appendix B Verilog 327

Appendix C Shared variable packages 333

Bibliography 339

Answers to selected exercises 341

Index 363