Digital Integrated Circuit Design using Verilog and Systemverilog

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Название: Digital Integrated Circuit Design using Verilog and Systemverilog

Автор: Mehler R.

Издательство: Newnes, Elsevier Inc

Год: 2015

Страниц: 445

ISBN: 978-0-12-408059-1, 9780124095298

Формат: PDF

Размер: 70 Мб

Язык: English

This is a book about using Verilog and SystemVerilog to design digital-integrated circuits. It takes the readers from the most fundamental elements of digital design through the design of sophisticated components and interfaces. Included are guidelines for optimizing designs and creating robust, reliable systems.

Digital-integrated circuits are the electronic brains behind all modern electronics.

Communications, computers, aviation, automobiles, consumer appliances, and much more: if it runs on electricity, it has digital-integrated circuits someplace in the background. All modern digital circuits are designed with a hardware description language, and Verilog/SystemVerilog is the engineer’s choice for the majority of new designs.

Beyond simply a language reference manual, this book not only teaches the syntax of Verilog/SystemVerilog hardware description language, it teaches how to effectively use it to produce optimized circuits that will work the first time, every time. It contains little-understood information on asynchronous interfaces, a common source of failure in digital designs, and a guide to design partitioning to produce optimal designs.

While no prior exposure to any hardware description language is expected, readers should have some basic knowledge of Boolean algebra and electrical engineering fundamentals such as Ohm’s law.

This book is based on courses taught by the author at California State University. The courses are themselves based on the author’s 20 years of experience in private industry designing digital circuits prior to joining the CSU faculty.

Introduction

Bottom-up design

Behavioral coding part I: blocks, variables, and operators

Behavioral coding part II: defines, parameters, enumerated types, and packages

Behavioral coding part III: loops and branches

Subroutines and interfaces

Synchronization

Simulation, timing, and race conditions

Architectural choices

Design for testability

Library modeling

Design examples

A: SystemVerilog keywords

B: Standard combinational and sequential functions

C: Number systems